1. Field of the Invention
The invention relates generally to the field of integrated circuit chips for use in digital data processing systems, and more specifically to random access memory (RAM) chips used in various portions of such systems to store digital data for processing or other purposes, such as control or the like.
2. Description of the Prior Art
Modern digital data processing systems, that is, computer systems, typically use a large number of random access memory (RAM) chips to store data and other information for use in processing and control of such systems. In addition to using them in main memories, modern computer systems also use RAM chips in cache memories, that is, relatively small, high speed data storage subsystems connected directly to an associated central processing unit (CPU) by a private bus and accessible primarily thereby. Random access memory chips are also used in, for example, translation buffers in the CPU that are used in translating from virtual to physical addresses in computer systems employing virtual memory techniques. RAM chips may also be used in, for example, writable control stores used to store microcode sequences for processing of instructions, and in similar data storage areas in the CPUs.
A major problem with current random access memory chips is that they require the external circuitry to supply a number of input signals having fairly complex relative timing requirements and to maintain them in the required conditions throughout the storage or retrieval operation in order to operate properly.
In current memory systems, the random access memory (RAM) chips receive data and address signals from a plurality of data and address registers, and also receive read/write and depending on the particular chips, other operation control signals. If the required operation is a read operation, the RAM also transmits the read data to a data output register, which latches the read data and makes it available to other circuitry in the computer system. The operation of the memory system is limited by the potential skew of the numerous signals transmitted to and from the RAM, by the set-up times required for the signals to shift, if necessary, between negated and asserted conditions, and also by the circuit delays inherent in the operation of the circuits themselves. In current memory systems, the off-chip registers and control signal generation circuitry must maintain the address, data (if a write operation) and control signals at the required levels during the entire memory operation.